1. Field of the Invention
The present invention relates to a protection means for preventing power-on sequence induced latch-up, and more particularly to a protection means for preventing power-on sequence induced latch-up and having low coupling effect of the capacitor and adapted to be integrated with other semiconductor devices on the same semiconductor substrate.
2. Description of the Related Art
In a CMOS, the latch-up effect always bothers many layout designers because the effect can cause the device failure temporarily or even forever and can affect the reliability of devices in the CMOS.
In the application of CMOS""s with multiple power sources, the power-on sequence is one possible cause that induces the latch-up effect. The latch-up effect induced by power-on sequence and conventional methods for preventing the latch-up effect will now be described.
Referring to FIG. 1, the N-well and its overlaying layers of a conventional CMOS comprises a p-type substrate 11, an N-well 12, the source 13 of PMOS that is electrically connected to a second power supply VDD2, and an N+ region 14 that connects the N-well 12 to a first power supply VDD1. In this structure, the voltage of VDD1 must be higher than that of VDD2 to prevent the pn junction between source 13 and N+ region 14 from being forward biased.
However, when the device as described above operates, some problems can be caused by the power-on sequence. For example, in the normal operation mode, if the power of VDD2 is provided before that of VDD1, the pn junction between source 13 and N+ region 14 is always reverse biased when a voltage is applied to the source 13. Therefore, the operation of the CMOS is normal without power-on sequence induced latch-up effect. However, if the power of VDD1 is provided before that of VDD2, the pn junction between source 13 and N+ region 14 is forward biased for a short period of time after a voltage is applied to the N+ region 14. For example, if the voltage of VDD1 is 3.3V and that of VDD2 is 2.5V, it can take a short period of time, for example about several mini seconds, for the voltage of N+ region 14 VDD1 to reach the maximum value of 3.3V, as shown in FIG. 2. When the voltage of VDD1 is lower than that of VDD2 minus the forward bias of pn junction (about 2.0V in general), i.e. when VDD1 is applied for the initial time period of T1 as shown in FIG. 2, the pn junction between the source 13 and the N+ region 14 is forward biased.
As described above, when the voltage of VDD1 is lower than that of VDD2 minus the forward bias of pn junction, the pn junction between the source 13 and the N+ region 14 is forward biased. Therefore, a forward current flows across the junction of P+/N, and triggers the thyristor composed of parasitic transistor pnp and npn of the CMOS to turn on. This is the so-called latch-up effect and causes the failure of the CMOS device.
There are two conventional methods for preventing the latch-up effect. One of the m methods uses a resistor located and connected between the power supply of VDD1 and the corresponding pin of IC in order to limit the current flowing into the CMOS device so that the latch-up effect can be avoided. The other methods uses a capacitor located and connected between the power supply of VDD1 and the ground pin of IC in order to share a part of electric charge and make the current flowing into the CMOS device incapable of triggering the latch-up effect.
However, both of these two conventional methods for preventing power-on sequence induced latch-up effect use elements such as a resistor or a capacitor that is formed on the printed circuit board (PCB) and is not integrated in the same semiconductor substrate with the CMOS. Obviously, it is unsuitable for practical application. Furthermore, another disadvantage of these two conventional methods lies in that the external resistor or capacitor can make the circuit in IC unstable due to electromagnetic coupling.
Accordingly, an object of the present invention is to provide a protection means for preventing power-on sequence induced latch-up effect. The protection means has low capacitor coupling effect and is suitable to be integrated with other semiconductor device in the same semiconductor substrate.
To achieve the above-mentioned object, protection means for preventing power-on sequence induced latch-up is provided. The protection means is used in a power supply system having a first power supply and a second power supply wherein the voltage of the first power supply is higher than that of the second power supply. The protection means comprises:
a voltage-drop circuit having an input terminal and an output terminal, the input terminal being connected to the first power supply;
an inverter having an input terminal and an output terminal, the input terminal being connected to the output terminal of said voltage-drop circuit;
a switching NMOS transistor with the gate connected to the output terminal of said inverter and the source connected to ground; and
a variable capacitance circuit having a first capacitor and a second capacitor, the capacitance of the first capacitor being much larger than that of the second capacitor, the first terminal and the second terminal of the first capacitor being connected to the second power supply and the first terminal of the second capacitor respectively, the second terminal of the second capacitor being connected to ground, the common node of the second terminal of the first capacitor and the first terminal of the second capacitor being connected to the drain of said switching NMOS transistor,
wherein said switching NMOS transistor and said variable capacitance circuit are formed on the same semiconductor substrate.
Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.